Exemplary embodiments of the present invention relate to a semiconductor chip, a semiconductor package, and a method for manufacturing the semiconductor chip, and more particularly, to a semiconductor chip including a through-silicon via (TSV) with a plurality of sub vias, a semiconductor package, and a method for manufacturing the semiconductor chip for reducing open failures.
Modern electronic products are much smaller in size and higher in performance than before. With increased demands for mobile electronic products, the demand for ultra-small high-capacity semiconductor memory devices has increased. Increasing the storage capacity of the semiconductor memory device may include increasing the integration degree of a semiconductor chip or mounting and assembling a plurality of semiconductor chips within a single semiconductor package. The former high integration method may require much effort, capital, and time, but the latter packaging method accommodates easier way to increase the storage capacity of the semiconductor memory. The latter packaging method is very advantageous in terms of necessary capital, research, and development effort, and development time, as compared to the former method. Hence, semiconductor memory manufacturers have made many efforts to increase the storage capacity of the semiconductor memory device through a multi chip package which mounts a plurality of semiconductor chips within a single semiconductor package.
Examples of the method of mounting the plurality of semiconductor chips within the single semiconductor package include a method of mounting semiconductor chips horizontally, and a method of mounting semiconductor chips vertically. However, due to characteristics of electronic products which tend to be smaller in size, most semiconductor memory manufacturers prefer a stack type multi chip package in which semiconductor chips are stacked vertically. A stack chip package technique can reduce manufacturing costs of a package due to a simplified process and is advantageous to mass production. However, the stack chip package technique has a disadvantage in that an interconnection space for internal electrical connection of the package is insufficient due to the increase in the number and size of stacked chips. Considering these points, a package structure using a through-silicon via (TSV) has been proposed as one example of a stack package. Such a package is manufactured by forming TSVs within chips at a wafer level and coupling the chips physically and electrically in a vertical direction by the TSVs.
In general, a TSV is formed in correspondence to a chip pad of a semiconductor chip. In this case, an open failure occurring in a TSV may result in an entire failure of a semiconductor chip or a semiconductor package. The open failure of the TSV may be solved by widening the width (cross-sectional area) of the TSV. However, since TSVs should not be formed where various semiconductor devices are formed, there is a limit to widening the width (cross-sectional area) of the TSVs.